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[SCM] kx_8051

Description: M8051内核编译好的，接上rom和ram就可以可以直接使用。据说最高支持200M时钟！-M8051 compiled kernel, with access to the rom and ram can be used directly. The maximum clock is said to support the 200M!
Platform: | Size: 5113856 | Author: 1987 | Hits:

[Embeded-SCM Develop] DoubleDort_RAM

Description: 双口RAM控制时序仿真 双口RAM控制时序仿真 -Control of dual-port RAM dual-port RAM timing simulation control timing simulation to control dual-port RAM Timing Simulation
Platform: | Size: 1350656 | Author: wangzhaohui | Hits:

[Embeded-SCM Develop] TESTRAM

Description: FPGA，双口RAM测试程序，仿真双口RAM工作时序，对时序的理解！适合对双口RAM不太了解的初学者使用！QUARTUSII8.0软件平台仿真通过！-FPGA, dual-port RAM testing procedures, simulation of dual-port RAM timing work, the understanding of the timing! Suitable for dual-port RAM of the beginners do not know much about the use of! Simulation software platform QUARTUSII8.0 through!
Platform: | Size: 447488 | Author: wangzhaohui | Hits:

[VHDL-FPGA-Verilog] TLC5510_IIPRAM1

Description: FPGA控制双口RAM、实现TLC5510采样控制双口RAM读写！QUARTUS II8.0平台仿真验证通过，并在硬件上运行通过测试！-FPGA control of dual-port RAM, the realization of sampled-data control TLC5510 dual-port RAM read and write! QUARTUS II8.0 platform through simulation and hardware to run through the test!
Platform: | Size: 3439616 | Author: wangzhaohui | Hits:

[VHDL-FPGA-Verilog] mem_ctrl_latest.tar

Description: 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
Platform: | Size: 331776 | Author: zhangsan | Hits:

[Windows Develop] fifo_design

Description: 异步fifo的设计，能够很好的的完成，数据的缓冲，内部有ram存储器-The design of asynchronous fifo， Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory
Platform: | Size: 2048 | Author: 孟霑 | Hits:

[VHDL-FPGA-Verilog] TechXclusives-ReconfiguringBlockRAMs

Description: Xilinx FPGA block RAM reconfig via JTAG
Platform: | Size: 104448 | Author: Kraja | Hits:

[VHDL-FPGA-Verilog] spmem.tar

Description: Sinlge port RAM VHDL/Verilog design
Platform: | Size: 1024 | Author: Ravi | Hits:

[Other] ram

Description: 代码实现了一个由32位寄存器组成的寄存器组，并有多个控制输入和两个输出，方便使用。-The code implements a 32-bit register consisting of registers, and there are multiple control inputs and two outputs, easy to use.
Platform: | Size: 10240 | Author: Pang scotto | Hits:

[VHDL-FPGA-Verilog] testRAMWR

Description: 这是一个用VHDL编写的读写双口RAM的程序.-This is a work written in VHDL to read and write dual-port RAM program.
Platform: | Size: 1068032 | Author: chenye | Hits:

[Software Engineering] spartan6_fpga_blockram_user_guide

Description: Spartan6　FPGA中的块存储器使用指南，可以构建为FIFO，ROM，RAM，移位寄存器等。-Spartan6 FPGA block memory in the User Guide, you can build for FIFO, ROM, RAM, shift registers and so on.
Platform: | Size: 376832 | Author: james | Hits:

[VHDL-FPGA-Verilog] components

Description: quartus的几个IP核（PWM,RAM,I2C）-quartus several IP core (PWM, RAM, I2C)
Platform: | Size: 226304 | Author: 宋瑞 | Hits:

[VHDL-FPGA-Verilog] bram_delay

Description: Verilog编写的代码，单口RAM用程序控制地址，而不是在仿真文件里面控制地址-Verilog code is written, single-port RAM with the process control address, rather than inside the control address of the simulation file
Platform: | Size: 1438720 | Author: niuniu | Hits:

[VHDL-FPGA-Verilog] dpRam1

Description: Dual port ram design project developed in Xilinx using VHDL
Platform: | Size: 741376 | Author: qaziguy | Hits:

[Embeded-SCM Develop] DW8051

Description: 8051Ip核内部ram。很多8051iP核都没有内部ram，上传一个希望对大家有用-internel ram of 8051Ip
Platform: | Size: 73728 | Author: 刘超 | Hits:

[VHDL-FPGA-Verilog] dual_RAM

Description: vhdl语言编写的双口ram及testbench,模块可以在modelsim里进行时序和功能仿真。-vhdl language of the dual-port ram, and testbench, modules, conducted in the modelsim timing and functional simulation.
Platform: | Size: 1024 | Author: 易凯 | Hits:

[VHDL-FPGA-Verilog] RAM.ZIP

Description: VHDL CODE FOR RAM AND ROM
Platform: | Size: 1024 | Author: praba | Hits:

[VHDL-FPGA-Verilog] BS

Description: 用EDA设计ROM和RAM及其应用，用VHDL语言编程实现字符、汉字的存取并用点阵显示-ROM and RAM design with the EDA and its applications, using VHDL programming language characters, Chinese characters, access to and use dot-matrix display
Platform: | Size: 13039616 | Author: 黄奇家 | Hits:

[Other] jj

Description: 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采样和数据存储回放。经测试，系统整体指标良好，垂直灵敏度和扫描速度等各项指标均达到设计要求。-The problem to design a digital storage oscilloscope, to Xilinx, 200,000 FPGA chip as the core, supplemented by the necessary peripherals (including signal conditioning, sample and hold, internal trigger, A/D converter, D/A conversion and I/O modules) the use of VHDL language programming, arbitrary waveform one-shot, continuous playback is triggered, and storage, in accordance with the requirements of the vertical sensitivity and sweep speed of the gear set. Signal acquisition, it will be the external input signal conditioning by the signal conditioning modules to the A/D circuit input range, after A/D converted into the FPGA s internal dual-port RAM for high-speed cache, and the results through the D/A converter to give general oscilloscope shows completed, the low-frequency signals in real-time sampling and high-frequency signals equivalent sampling and data storage playback. Been tested, the system as a whole indices are good, the vertical sensitivity and scan speed indicators meet
Platform: | Size: 546816 | Author: 黄奇家 | Hits:

[VHDL-FPGA-Verilog] ahb_ram

Description: AHB接口的ram控制器，可靠性非常强。除了两个周期内发生读到写或写到读的极限情况（一般处理器设计中不会有这种传输方式），其他传输方式完全没有问题-AHB interface ram controller, reliability is very strong. In addition to occurring in two cycles read or write read write the limit (usually processor design will not have such means of transmission), other means of transmission is no problem
Platform: | Size: 1024 | Author: Jasking Wu | Hits:
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